Vetus Pars Tests

Here are all of the available tests for Vetus Pars. If you would like to add to this list please use the test submission form here Vetus Pars Test Submission . If you can’t find a test you need and are unable to create your own you can make a request in the forums and we can try to get one created for you when possible.

Chip / Part NumberTest NameTypeCompatible Chips / AliasesDescriptionSubmitterTest File
KM 4164B-12 KM4164B-12 W2R2 DRAM KM4164B-12 The test begin with a short address-line check and then exercise all 65,536 memory cells. The memory is treated as 256 rows × 256 columns.

Each row is tested in eight blocks of 32 columns. The display shows progress similar to:

Row 001 / 256
Col 032 / 256

2W2R test

This is the more thorough and longer-running test (see 1W1R for shorter).

• Writes a checkerboard pattern to every cell and verifies it
• Writes the inverse checkerboard pattern and verifies it
• Tests every cell once as 0 and once as 1
• Performs 131,072 writes and 131,072 verified reads

Each individual cell is tested at two logic values. A passing result therefore confirms full-address coverage, and that every cell can store both 0 and 1.		 Midwest Mac Download
KM 4164B-12 KM4164B-12 1W1R DRAM KM 4164B-12 The test begin with a short address-line check and then exercise all 65,536 memory cells. The memory is treated as 256 rows × 256 columns.

Each row is tested in eight blocks of 32 columns. The display shows progress similar to:

Row 001 / 256
Col 032 / 256

1W1R test - This is the shorter routine screening test (see 2W2R variant for longer).

• Writes one checkerboard value to every cell
• Reads and verifies that value
• Covers all 65,536 cells
• Performs 65,536 writes and 65,536 verified reads
• Alternates the checkerboard polarity by row, so half the cells are tested with 0 and half with 1

Each individual cell is tested at only one logic value. A passing result therefore confirms full-address coverage, but it does not prove that every cell can store both 0 and 1.		 Midwest Mac Download
CD74HCT20E CD74HCT20E 7400 Series CD74HCT20E CD74HCT20E Test Overview

DeviceCD74HCT20E is a 14-pin, dual 4-input NAND gate. It contains two independent four-input NAND gates.

What this CHIP file tests file tests all sixteen possible input combinations, from 0000 through 1111, on both gates.4-input NAND output must be LOW only when all four inputs are HIGH. It must be HIGH for the other fifteen combinations. Any unexpected output marks the test as FAILED.

What it can find test checks every input path on both gates and is intended to catch common stuck-output, missing-input, and wrong-function faults.

Important limits are basic functional screening tests for a 5 V logic IC. A PASSED result means the programmed static logic checks completed successfully; it does not prove timing, propagation delay, threshold margins, output-current capability, leakage, ESD robustness, or operation under all real circuit loads.

Safe use the exact part number, DIP orientation, pin count, and socket placement before starting. Do not insert, remove, or rotate a device while a test is running. The CHIP file uses ASAFE at the beginning and before normal completion to release tester-controlled socket lines to a high-impedance safe state.		 mbrando Download
CD74HCT00E CD74HCT00E 7400 Series CD74HCT00E CD74HCT00E Test Overview

DeviceCD74HCT00E is a 14-pin, quad 2-input NAND gate. It contains four independent logic gates.

What this CHIP file tests file tests all four NAND gates. For each gate, it applies the four possible two-input combinations: 00, 01, 10, and 11.NAND output must be HIGH for 00, 01, and 10. It must be LOW only when both inputs are HIGH (11). Any unexpected output marks the test as FAILED.

What it can find test is intended to catch common functional faults such as a stuck output, a missing input path, an incorrect gate function, or many internal connection failures.

Important limits are basic functional screening tests for a 5 V logic IC. A PASSED result means the programmed static logic checks completed successfully; it does not prove timing, propagation delay, threshold margins, output-current capability, leakage, ESD robustness, or operation under all real circuit loads.

Safe use the exact part number, DIP orientation, pin count, and socket placement before starting. Do not insert, remove, or rotate a device while a test is running. The CHIP file uses ASAFE at the beginning and before normal completion to release tester-controlled socket lines to a high-impedance safe state.		 mbrando Download
CD74HCT11E CD74HCT11E 7400 Series CD74HCT11E CD74HCT11E Test Overview

DeviceCD74HCT11E is a 14-pin, triple 3-input AND gate. It contains three independent AND gates.

What this CHIP file tests file tests every input state from 000 through 111 on each of the three gates.AND output must be HIGH only when all three inputs are HIGH. It must be LOW for the other seven input combinations. Any unexpected output marks the test as FAILED.

What it can find test is intended to catch stuck-high or stuck-low outputs, missing or shorted input paths, and incorrect gate-function faults.

Important limits are basic functional screening tests for a 5 V logic IC. A PASSED result means the programmed static logic checks completed successfully; it does not prove timing, propagation delay, threshold margins, output-current capability, leakage, ESD robustness, or operation under all real circuit loads.

Safe use the exact part number, DIP orientation, pin count, and socket placement before starting. Do not insert, remove, or rotate a device while a test is running. The CHIP file uses ASAFE at the beginning and before normal completion to release tester-controlled socket lines to a high-impedance safe state.		 mbrando Download
CD74HC283E CD74HC283E 7400 Series CD74HC283E CD74HC283E Test Overview

DeviceCD74HC283E is a 16-pin, 4-bit binary full adder. It accepts two 4-bit input words plus carry-in and produces a 4-bit sum plus carry-out.

What this CHIP file tests file applies six arithmetic vectors: zero plus zero, a simple one-bit addition, a multi-bit addition without carry-out, an addition with carry-out, an addition using carry-in, and a maximum-value addition case.each vector, it checks all four sum outputs and the carry-out output. Any output that differs from the expected arithmetic result marks the test as FAILED.

What it can find test is intended to catch common stuck-bit faults, input/output wiring faults, carry-in faults, carry-out faults, and gross arithmetic-logic failures.

What it does not exhaustively test file does not apply all 512 possible combinations of A, B, and carry-in. It is a practical functional screen rather than a complete truth-table or speed test.

Important limits are basic functional screening tests for a 5 V logic IC. A PASSED result means the programmed static logic checks completed successfully; it does not prove timing, propagation delay, threshold margins, output-current capability, leakage, ESD robustness, or operation under all real circuit loads.

Safe use the exact part number, DIP orientation, pin count, and socket placement before starting. Do not insert, remove, or rotate a device while a test is running. The CHIP file uses ASAFE at the beginning and before normal completion to release tester-controlled socket lines to a high-impedance safe state.		 mbrando Download
CD74HC175E CD74HC175E 7400 Series CD74HC175E CD74HC175E Test Overview

DeviceCD74HC175E is a 16-pin, quad positive-edge-triggered D-type flip-flop with a common active-low reset. Each channel has a Q output and a complementary Q-bar output.

What this CHIP file tests file first asserts the common reset and verifies that all Q outputs are LOW and all Q-bar outputs are HIGH.then releases reset, applies the D-input pattern 1010, creates a rising clock edge, and verifies that the Q outputs store 1010 while the Q-bar outputs store the inverse pattern 0101. Any unexpected output marks the test as FAILED.

What it can find test is intended to catch common reset, clock, data-storage, normal-output, and complementary-output faults.

What it does not exhaustively test file does not test every possible data pattern or characterize setup time, hold time, clock-to-output delay, reset recovery, or maximum clock frequency.

Important limits are basic functional screening tests for a 5 V logic IC. A PASSED result means the programmed static logic checks completed successfully; it does not prove timing, propagation delay, threshold margins, output-current capability, leakage, ESD robustness, or operation under all real circuit loads.

Safe use the exact part number, DIP orientation, pin count, and socket placement before starting. Do not insert, remove, or rotate a device while a test is running. The CHIP file uses ASAFE at the beginning and before normal completion to release tester-controlled socket lines to a high-impedance safe state.		 mbrando Download
CD74HCT245E CD74HCT245E 7400 Series CD74HCT245E CD74HCT245E Test Overview
This .chip file is a basic functional test for a CD74HCT245E / 74HCT245 20-pin octal bus transceiver in a DIP-20 socket.

It tests the chip in both data directions:

A-to-B direction: Sets DIR high and enables outputs with active-low OE.
Drives the A bus with four patterns: 00, FF, 55, and AA.
Reads the B bus after each pattern and checks that it matches.
B-to-A direction: Sets DIR low, keeps outputs enabled, and repeats the same four patterns.
Drives the B bus and verifies that the A bus matches.
The patterns check:

All outputs low (00)
All outputs high (FF)
Alternating bits (55)
The opposite alternating bits (AA)
At the end, the program disables the transceiver output by taking OE high, returns both buses to input mode, executes ASAFE, and reports PASS. If any expected bus value does not match, it executes ASAFE, reports FAIL, and stops.

What it does not test
It does not prove that the outputs are truly high impedance when OE is high. A reliable Hi-Z test needs external pull-up/pull-down resistors or other fixture support.
It does not measure output voltage levels, current drive capability, propagation delay, leakage, or timing specifications.
It does not identify counterfeit or marginal parts that happen to pass these static logic patterns.
It does not provide a batch/pass counter or automatic “remove/insert next” loop. The tested counter/restart approach was not reliable on the current firmware, so this version uses the normal result-screen workflow.
The file is intended as a practical go/no-go functional screen, not a complete production-characterization test. Before removing or inserting a device, wait for the normal test result and use the tester’s standard navigation; ASAFE releases tester-controlled socket I/O lines, but it should not be assumed to remove any automatic socket supply rail without confirming that behavior on the specific hardware.		 mbrando Download
KM59100 KM591k-sz DRAM — This test is for 30 pin SIMM RAM and requires the 30 pin SIMM add-on. This test will return the size of the RAM module based on how many addresses are available. NIVBOT Download
KM59100 KM591k-rnd DRAM — This is a test for 30 pin SIMM DRAM. It picks a random row and checks every column address in that row. It requires the 30 pin SIMM add-on board. NIVBOT Download
HCF4001B HCF4001B 7400 Series — — NIVBOT Download
44256 44256 DRAM — — NIVBOT Download
41256 41256 DRAM — — NIVBOT Download
6502 6502-life CPU — Just a quick test to see if reset works and the CPU is responsive. NIVBOT Download
6502 6502-jmp CPU — This test is for the 6502 not the variants. It resets the CPU then sends JMP after reset and goes to the coded jump address. NIVBOT Download
4464 RAM 4464-sp DRAM — sp - for speedy. It's a little faster but not as deep of a test. NIVBOT Download
4464 RAM 4463-ex DRAM — This is an extended full test of each address is takes a while to complete NIVBOT Download
4416 RAM 4416-sp DRAM — This test is quicker but not a full deep test of each address NIVBOT Download
4416 RAM 4416 RAM DRAM — — NIVBOT Download
4164 4164-ras DRAM — This test only tests the RAS line. NIVBOT Download
4164 4164-cas DRAM — This test only tests the CAS line. NIVBOT Download
4164 RAM 4164 RAM DRAM — — NIVBOT Download
2114 RAM 2114 RAM SRAM — — NIVBOT Download
74LS373 74LS373 7400 Series — — NIVBOT Download
74LS273 74LS273 7400 Series — — NIVBOT Download
74LS257 74LS257 7400 Series — — NIVBOT Download
74LS245 74LS245 7400 Series — — NIVBOT Download
74LS244 74LS244 7400 Series — — NIVBOT Download
74LS166 74LS166 7400 Series — — NIVBOT Download
74LS161 74LS161 7400 Series — — NIVBOT Download
74LS157 74LS157 7400 Series — — NIVBOT Download
74LS138 74LS138 7400 Series — — NIVBOT Download
74LS93 74LS93 7400 Series — — NIVBOT Download
74LS86 74LS86 7400 Series — — NIVBOT Download
74LS74 74LS74 7400 Series — — NIVBOT Download
74LS32 74LS32 7400 Series — — NIVBOT Download
74LS14 74LS14 7400 Series — — NIVBOT Download
74LS04 74LS04 7400 Series — — NIVBOT Download
74LS08 74LS08 7400 Series — — NIVBOT Download
74LS02 74LS02 7400 Series — — NIVBOT Download
74LS00 74LS00 7400 Series — — NIVBOT Download